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THE TECHNOLOGY

GaAs-on-SiC Heterogeneous Integration

ISRONIX is developing a heterogeneous semiconductor integration platform

that combines a thin GaAs active device region with a high-thermal-conductivity

SiC substrate.

By creating a more efficient thermal path from the active region into the SiC substrate, 

the platform is designed to reduce device temperature and provide greater thermal operating headroom for high-power and high-frequency applications.

This integration approach establishes a foundation for next-generation GaAs RF

power devices with improved thermal performance, higher power density potential,

and enhanced reliability.

THERMAL LIMITATIONS OF CONVENTIONAL GaAs

THERMAL BOTTLENECK

Heat at the Active Region

In conventional GaAs pHEMTs, heat is concentrated near the gate region

and must travel through materials with limited thermal conductivity.

As device power increases, this localized thermal resistance raises channel temperature, restricting power density, linearity and long-term reliability.

Because the heat originates within a highly localized active region, conventional cooling approaches cannot fully eliminate the thermal bottleneck.

Overcoming this limitation requires a more efficient heat extraction path directly from the active device region.

OUR APPROACH

Engineering a more direct thermal path from the active region into SiC
DIRECT THERMAL PATH

ISRONIX is engineering a shorter thermal path between the GaAs active

region and the high-thermal-conductivity SiC substrate, aiming to improve

heat extraction efficiency.

HEAT SPREADING INTO SiC

The high thermal conductivity of SiC spreads heat laterally and vertically, reducing localized thermal concentration and improving heat removal

from the active region.

INTEGRATED THERMAL ARCHITECTURE

ISRONIX integrates the GaAs device structure with a high-thermal-conductivity SiC substrate, creating a shorter and more efficient path for heat extraction from the active region.

DEVELOPMENT PATHWAY

From interface engineering to device-level validation

01 · INTERFACE ENGINEERING

Engineer and optimize the GaAs–SiC
integration interface for thermal and
structural performance.

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02 · BONDING & INTEGRATION

Develop and refine the bonding process to create a robust GaAs–SiC integrated structure.

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03 · PROCESS DEVELOPMENT

Establish reproducible processes to advance integrated structures toward functional RF devices.

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04 · DEVICE VALIDATION

Fabricate and evaluate test structures to validate electrical, thermal and RF performance.

TARGET PLATFORM

GaAs-on-SiC for next-generation RF power devices

ISRONIX is developing a heterogeneous GaAs-on-SiC platform that combines the RF performance of GaAs with the superior thermal conductivity of SiC through an engineered integration interface, enabling more efficient heat extraction and higher power density.